The present invention relates, in general, to an integrated-circuit, memory device, such as a DRAM (dynamic random access memory). More particularly, the present invention relates to an integrated circuit in which a DRAM, or other memory device, is mounted directly onto a logic chip. In one implementation, the mounting is formed using chip-on-chip technology, thereby obviating the need for bond wiring, conventionally used to connect separate memory and logic chips.
Through the use of flip-chip technology which utilizes bond pads by which to form connections in a multi-chip, integrated-circuit package, interconnections formed between the memory device and the logic chip are of substantially reduced levels of capacitance. Such reduced levels of capacitance, reduce amounts of power required to operate a circuit formed of the memory and logic chips. Also, such reduced levels of capacitance permits the circuit to be operated at increased speeds.
Integrated circuit memory devices are used in many electronic systems. Such memory devices provide storage of data necessary to the function of the electronic system. One or more non-memory integrated circuits of the electronic system access the data stored in the memory devices.
Different types of integrated circuit memory devices are used to meet the different requirements of electronic systems. ROM (Read Only Memory), EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), SRAM (Static Random Access Memory) and DRAM are among the integrated circuit memory types commonly used in electronic systems.
DRAM (Dynamic Random Access Memory) is generally used in applications which require low cost, large amounts of data storage and fast read and write access to the data. SRAM is generally faster but more expensive than DRAM. EEPROM is nearly the same cost as DRAM but the write access is not random and is too slow for many applications. EPROM can be erased only by exposure to ultraviolet light and otherwise can be written only once and cannot be used for most applications. ROM is hard wired with data and can only be read and cannot be used if writing data to the memory is required. The general utility of DRAM has resulted in DRAM being the most common type of integrated circuit memory.
As the non-memory integrated circuits increase in speed it is desirable to have the memory integrated circuits increase in speed. DRAM speed has been increased by improvements in the definition of how the DRAM interfaces to non-memory integrated circuits. These interface definitions include FPM (Fast Page Mode), EDO (Extended Data Out), SDRAM (Synchronous DRAM) and DDRSDRAM (Double Data Rate DRAM). Each of these interface definitions has allowed the DRAM to output data at progressively faster rates.
In addition, DRAM speeds have been increased by increasing the number of bits the DRAM outputs at a time or the width of the output. The amount of data a memory can output is determined by the output width multiplied by the output data rate.
The inductance and capacitance associated with connecting an integrated circuit in one package to an integrated circuit in another package create problems if the data transfer rate is high. In order to solve these problems many interface standards have been developed including TTL, LVTTL and SSTL. These interface standards use a reference voltage connected via a load resistor to each output node. The voltage swing of the output is restricted but extra power is consumed since any current through the load resistor is wasted. As the data output rate increases, the drive of the output circuits must be increased so that the capacitance on the outputs can be charged or discharged more quickly. This causes the voltage swing on the output to increase which causes more power to be consumed through the load resistor.
Reducing both the inductance and capacitance on data outputs would allow higher data transfer rates. One packaging technology which reduces the inductance and capacitance on data outputs is referred to as Flip Chip mounting wherein an integrated circuit is mounted (face down) directly to a printed circuit board. This eliminates inductance and capacitance associated with bond wires and package lead frame but the capacitance and inductance associated with the printed circuit board remains.
Integrated circuit technology advances are enabling more components of an electronic system to be contained on one integrated circuit. Integration of more components of an electronic system into one integrated circuit generally reduces cost of the system. The cost reduction results from reduced power, reduced size and reduced assembly complexity. This cost reduction makes integrating memory and non-memory chips into the same integrated circuit desirable.
Integrating memory and non-memory circuits into the same integrated circuit chip incurs a cost penalty. The cost penalty is due to memory and non-memory circuits having different process requirements. The differing processing requirements can be explained, e.g. with respect to an example in which a pmemory is formed of a DRAM and a non-memory circuit is formed of a logic circuit.
A DRAM consists of an array of memory elements. Each element consists of a capacitor and a transistor. During the DRAM operation, a voltage level (a high voltage for a data 1, a low voltage for a data 0) is placed on the capacitor and the gate of the transistor is forced to a voltage which turns the transistor off. The data can then be read at a later time by turning the transistor on and sensing the voltage stored on the capacitor. Sensing the voltage requires the capacitance value of the capacitor to be adequate. The voltage on the capacitor will change due to leakage so the data must be read and rewritten frequently to prevent data loss. For a given leakage value the rate of change of the voltage stored on the capacitor is inversely proportional to the capacitance of the capacitor. Therefore the capacitance of the capacitor must be large enough to allow adequate refresh time (i.e., time between refreshes). Also, the leakage from the capacitor must be minimized to provide adequate refresh time. The DRAM capacitor and the very low leakage requirement are unique to the DRAM and are not required by the logic circuit.
A logic circuit requires more levels of interconnect than a DRAM. Advanced DRAMs use two levels of metal interconnect while advanced logic circuits use four or five levels of interconnect. A logic circuit requires the highest performance transistors possible to insure adequate performance of the logic circuit but there is not a requirement for the low leakage levels of a DRAM. Therefore, the logic transistor is designed differently with respect to gate oxide thickness, source and drain doping profiles and isolation than the DRAM transistor.
The differences listed above and others have resulted in DRAM and logic processes being quite different. When DRAM and logic is combined onto a single integrated circuit the process required is significantly more complicated than either the DRAM process or the logic process.
It is in light of this background information that the significant improvements of the present invention have evolved.
The present invention, accordingly, advantageously provides a multi-chip device, and an associated method, in which a memory integrated circuit, such as a DRAM, is mounted directly onto a non-memory integrated circuit, such as a logic chip.
In such a manner, the need for the bond wires, lead frames and printed circuit board traces conventionally used to connect separate memory and non-memory chips, is obviated. Formation of a multi-chip package through the use of chip-on-chip technology permits interconnects between the memory and non-memory chip to be formed which exhibit substantially reduced levels of capacitance and inductance. The levels of capacitance and inductance are reduced to levels such that the interfaces formed by the connections between the memory and non-memory chips appear to the respective chips to be internal nodes of such chips.
Reduction in the levels of capacitance of the interconnections between the non-memory chip and memory chip reduces the power required to transfer data at a given rate between the non-memory chip and the memory chip.
Reduction in the levels of capacitance and -U inductance of the interconnections between the non-memory chip and memory chip increases the rate at which data transfer between non-memory chip and memory chip can occur without problems associated with ringing which require specialized interfaces such as TTL, LVTTL or SSTL.
In one implementation, the memory integrated circuit is a DRAM memory chip. The DRAM memory chip is mounted, using technology similar to flip chip technology, upon a logic chip such that bond pads of the DRAM memory chip are connected to the bond pads of the logic chip with solder or gold bumps or balls.
Said gold or solder bumps or balls provide all electrical interconnection between the memory and logic chips including power, control and data exchange. Circuits used to drive interconnections between memory and logic chips are distinguished by being designed to drive only loads associated with the small capacitance associated with this chip-on-chip assembly. Further, interconnections between memory and logic chips are driven to full power and ground levels, obviating the need for specialized interfaces such as TTL, LVTTL or SSTL.
In these and other aspects, therefore, a multi-chip integrated circuit package, and an associated method, is provided. The package includes a memory integrated circuit having a selected number of storage locations for storing data therein and having memory chip bond pads. A non-memory integrated circuit has bond pads for abutting together with the memory chip bond pads. An interconnector provides an electrical connection between the memory and non-memory chip bond pads.
A more complete appreciation of the present invention and the scope thereof can be obtained from the accompanying drawings which are briefly summarized below, the following detailed description of the presently-preferred embodiments of the invention, and the appended claims.